Emily Desjardins (25 September 2012). "JEDEC Announces Publication of DDR4 Standard". JEDEC . Retrieved 5 April 2019. Nilsson, Lars-Göran (2010-08-16). "DDR4 not expected until 2015". Semi accurate . Retrieved 2011-04-29. In the longer term, experts speculate that non-volatile RAM types like PCM ( phase-change memory), RRAM ( resistive random-access memory), or MRAM ( magnetoresistive random-access memory) could replace DDR4 SDRAM and its successors. [69]

In April 2013, a news writer at International Data Group (IDG)–an American technology research business originally part of IDC–produced an analysis of their perceptions related to DDR4 SDRAM. [43] The conclusions were that the increasing popularity of mobile computing and other devices using slower but low-powered memory, the slowing of growth in the traditional desktop computing sector, and the consolidation of the memory manufacturing marketplace, meant that margins on RAM were tight. DDR4 was expected to represent 5% of the DRAM market in 2013, [2] and to reach mass market adoption and 50% market penetration around 2015; [2] as of 2013, however, adoption of DDR4 had been delayed and it was no longer expected to reach a majority of the market until 2016 or later. [38] The transition from DDR3 to DDR4 is thus taking longer than the approximately five years taken for DDR3 to achieve mass market transition over DDR2. [33] In part, this is because changes required to other components would affect all other parts of computer systems, which would need to be updated to work with DDR4. [39]

Do I need DDR4 RAM 2666MHz memory?

In January, Samsung announced the completion and release for testing of a 2GB [1] DDR4 DRAM module based on a process between 30 and 39 nm. [30] It has a maximum data transfer rate of 2133 MT/s at 1.2V, uses pseudo open drain technology (adapted from graphics DDR memory [31]) and draws 40% less power than an equivalent DDR3 module. [30] [32]

i22f44600-ds-aksb-a.akamaihd.net, i22f47c00-ds-aksb-a.akamaihd.net, i22f4a100-ds-aksb-a.akamaihd.net, i22f55c00-ds-aksb-a.akamaihd.net, i22f5ca00-ds-aksb-a.akamaihd.net, i22f6b100-ds-aksb-a.akamaihd.net, i22f7bf00-ds-aksb-a.akamaihd.net, i22fdb800-ds-aksb-a.akamaihd.net, i22fdd700-ds-aksb-a.akamaihd.net, i3430c200-ds-aksb-a.akamaihd.net, i34d04400-ds-aksb-a.akamaihd.net, i34d71700-ds-aksb-a.akamaihd.net, i36486200-ds-aksb-a.akamaihd.net, i364b2700-ds-aksb-a.akamaihd.net, In 2008 concerns were raised in the book Wafer Level 3-D ICs Process Technology that non-scaling analog elements such as charge pumps and voltage regulators, and additional circuitry "have allowed significant increases in bandwidth but they consume much more die area". Examples include CRC error-detection, on-die termination, burst hardware, programmable pipelines, low impedance, and increasing need for sense amps (attributed to a decline in bits per bitline due to low voltage). The authors noted that, as a result, the amount of die used for the memory array itself has declined over time from 70–78% for SDRAM and DDR1, to 47% for DDR2, to 38% for DDR3 and to potentially less than 30% for DDR4. [50]As in DDR3, A12 is used to request burst chop: truncation of an 8-transfer burst after four transfers. Although the bank is still busy and unavailable for other commands until eight transfer times have elapsed, a different bank can be accessed. In April, Hynix announced that it had developed the world's first highest-density 128GB module based on 8 Gbit DDR4 using 20nm technology. The module works at 2133MHz, with a 64-bit I/O, and processes up to 17GB of data per second.